The present invention relates generally to enabling and disabling DQS signals, and more particularly to enabling and disabling DQS signals such that spurious DQS edges do not cause false clocking at the end of a DQS postamble or between back-to-back non-consecutive reads.
Memory interface circuits have become very important in integrated circuits including programmable circuits such as field programmable gate arrays (FPGAs). The data rates of these interfaces have increased greatly, particularly as new double-data-rate standards such as DDR2 and DDR3 have come into use. This increase in data rate has greatly increased the requirements on the timing of signals at the memory interface circuits.
During a data read from memory, these memory interfaces typically receive a number of groups of signals, each group including a number of data or DQ signals and a data strobe or DQS signal, which may be single ended or differential. The DQS signal is generally provided on a bidirectional bus. At the end of a read transaction, the driver providing the DQS signal returns to high impedance state. As a result, the voltage levels sensed may be indeterminate, potentially generating spurious edges of DQS in the receiving device or devices.
The reception of data is typically followed by a postamble period. At the end of this postamble period, the DQS drivers return to the high-impedance state. When the DQS pins are at an intermediate voltage, an input register clocked by the DQS signal may receive one or more spurious clock pulses. Also, at the end of a postamble period, a second back-to-back non-consecutive read may occur. The start of the second read may also cause the input register to receive one or more spurious clock pulses.
Timing complications arise not only with signals external to the memory interface, but with internal signals as well. For example, in an FPGA, enable signals that gate a DQS signal typically originate in its core circuits. These enable signals need to be provided to input/output circuits that may be an indeterminate distance from the core circuits. This leads to uncertainty in signal routing between the core and input/output circuits, which leads to uncertainty in the timing of the signals arrival the input/output circuits from the core.
Thus, what is needed are circuits, methods, and apparatus that can be controlled to isolate an input register or registers from spurious transitions on a DQS signal, both at the end of a DQS postamble and at the start of a back-to-back non-consecutive read. It is also desirable that these circuits, methods, and apparatus ease the transfer of DQS enable signals from a core to input/output circuits.